As semiconductor devices become more highly integrated, a transistor may be formed with a line width having a micro-size. In this regard, “hot carrier effects” may occur in the transistor.
Hot carrier effects may include a phenomenon in which a horizontal electric field is largely concentrated on a drain area when a length of a channel is short. Accordingly, electrical characteristics of a drain area may be degraded and holes may be discharged toward a substrate.
In addition, electrons may be trapped at lower portions of a gate oxide layer or a spacer. This may have an effect upon a threshold voltage.
Such hot carrier effects may occur when a high electric field is applied to the substrate even though a supply voltage may be low. This may be because a channel may have a short length due to the micro-size of the semiconductor device. In particular, this phenomenon may occur when the length of the channel, which may be a path of carriers, between a source area and a drain area is short.
To overcome the hot carrier effect, a transistor may use an LDD (Lightly Doped Drain) structure. On a semiconductor substrate, source/drain areas may be aligned on the substrate having a gate electrode between them. For an LDD structure, ion-implantation density of the source/drain areas may be low at an area in the vicinity of an edge of the gate electrode, and may be high at an area remote from the edge of the gate electrode. Such a layout may be a graded junction, and may reduce a sudden change of an electric field.
Hot carrier effects may be ameliorated or controlled by the LDD structure. As shown in FIG. 1, however, N− ions implanted into lower portions of side wall spacers that may be formed at the gate electrode may cause a problem if ion-implantation or ion-diffusion is performed relative to the drain or the source. In this case, a performance of the semiconductor device may still be degraded by the hot carrier effects.